The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 2018

Filed:

Jun. 17, 2016
Applicant:

Utac Thai Limited, Bangkok, TH;

Inventor:

Saravuth Sirinorakul, Bangkok, TH;

Assignee:

UTAC THAI LIMITED, Bangkok, TH;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/498 (2006.01); H01L 23/48 (2006.01); H01L 23/495 (2006.01); H01L 23/31 (2006.01); H01L 23/00 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 21/78 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49805 (2013.01); H01L 21/4825 (2013.01); H01L 21/4832 (2013.01); H01L 21/565 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 21/78 (2013.01); H01L 23/3114 (2013.01); H01L 23/3135 (2013.01); H01L 23/481 (2013.01); H01L 23/4952 (2013.01); H01L 23/49513 (2013.01); H01L 23/49524 (2013.01); H01L 23/49548 (2013.01); H01L 23/49568 (2013.01); H01L 23/49572 (2013.01); H01L 23/49579 (2013.01); H01L 23/49582 (2013.01); H01L 23/49816 (2013.01); H01L 24/73 (2013.01); H01L 24/97 (2013.01); H01L 2221/68381 (2013.01); H01L 2224/16245 (2013.01); H01L 2224/45144 (2013.01); H01L 2224/45147 (2013.01); H01L 2224/48091 (2013.01); H01L 2224/73265 (2013.01); H01L 2224/97 (2013.01); H01L 2924/01047 (2013.01); H01L 2924/12042 (2013.01); H01L 2924/15747 (2013.01); H01L 2924/181 (2013.01); H01L 2924/18301 (2013.01);
Abstract

A semiconductor package includes terminals, each having an exposed surface that is flush with a bottom surface of the semiconductor package, and a layer of interconnection routings disposed within the semiconductor package. At least one interconnection routing is electrically coupled with a terminal and extends planarly therefrom. The semiconductor package also includes at least one die coupled with the layer of interconnection routings. In some embodiments, the semiconductor package also includes one or more additional intermediary layers. Each intermediary layer includes a via layer and an associated routing layer. The associated routing layer includes associated routings. At least one associated routing is electrically coupled with a terminal and extends planarly therefrom. Each via layer couples two routing layers. The semiconductor package also includes a locking mechanism for fastening a package compound with the interconnection routings and the terminals.


Find Patent Forward Citations

Loading…