The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 20, 2018

Filed:

Sep. 30, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Christopher B. Wilkerson, Portland, OR (US);

Alaa R. Alameldeen, Hillsboro, OR (US);

Zeshan A. Chishti, Hillsboro, OR (US);

Jaewoong Sim, Atlanta, GA (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/122 (2016.01); G11C 7/10 (2006.01); G06F 3/06 (2006.01); G06F 12/0893 (2016.01);
U.S. Cl.
CPC ...
G06F 12/122 (2013.01); G06F 3/06 (2013.01); G06F 3/061 (2013.01); G06F 3/0644 (2013.01); G06F 3/0647 (2013.01); G06F 3/0673 (2013.01); G06F 12/0893 (2013.01); G11C 7/1072 (2013.01); G06F 2212/1016 (2013.01);
Abstract

An apparatus and method for implementing a heterogeneous memory subsystem is described. For example, one embodiment of a processor comprises: memory mapping logic to subdivide a system memory space into a plurality of memory chunks and to map the memory chunks across a first memory and a second memory, the first memory having a first set of memory access characteristics and the second memory having a second set of memory access characteristics different from the first set of memory access characteristics; and dynamic remapping logic to swap memory chunks between the first and second memories based, at least in part, on a detected frequency with which the memory chunks are accessed.


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