The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 13, 2018

Filed:

Feb. 27, 2017
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-Do, KR;

Inventors:

Sung-Uk Jang, Hwaseong-si, KR;

Gi-Gwan Park, Hwaseong-si, KR;

Ho-Sung Son, Hwaseong-si, KR;

Dong-Suk Shin, Yongin-si, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/265 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66545 (2013.01); H01L 21/265 (2013.01); H01L 29/6656 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

In a method of manufacturing a semiconductor device, an isolation pattern may be formed on a substrate to define a plurality of active patterns. The active patterns may protrude from the isolation pattern. A preliminary polysilicon layer may be formed on the active patterns to fill a gap between adjacent ones of the active patterns. Ions having no conductivity may be implanted into the preliminary polysilicon layer to form a polysilicon layer having no void. The active patterns maintain their crystalline state during the implanting of the ions. The polysilicon layer may be patterned to form a dummy gate structure on the active pattern. A source/drain region may be formed at an upper portion of the active patterns adjacent to sides of the dummy gate structure.


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