The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 13, 2018

Filed:

Jun. 13, 2016
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventors:

Shenqing Fang, Sunnyvale, CA (US);

Chun Chen, San Jose, CA (US);

Unsoon Kim, San Jose, CA (US);

Mark Ramsbey, Sunnyvale, CA (US);

Kuo Tung Chang, Saratoga, CA (US);

Sameer Haddad, San Jose, CA (US);

James Pak, Sunnyvale, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01); H01L 27/11573 (2017.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 27/11568 (2017.01); H01L 21/28 (2006.01);
U.S. Cl.
CPC ...
H01L 29/42344 (2013.01); H01L 27/11568 (2013.01); H01L 27/11573 (2013.01); H01L 29/66833 (2013.01); H01L 29/792 (2013.01); H01L 21/28282 (2013.01);
Abstract

A semiconductor device includes a substrate comprising a source region and a drain region, a bit storing element formed on the substrate, a memory gate structure, a first insulating layer formed on the substrate, a second insulating layer formed on the substrate, and a select gate structure formed on the first insulating layer. The second insulating layer is formed on the memory gate structure and the select gate structure and between the memory gate structure and the select gate structure.


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