The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 13, 2018
Filed:
Nov. 21, 2016
Applicant:
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Inventors:
Assignee:
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsin-Chu, TW;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 21/8234 (2006.01); H01L 29/78 (2006.01); H01L 29/786 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0886 (2013.01); H01L 21/823418 (2013.01); H01L 21/823431 (2013.01); H01L 21/823481 (2013.01); H01L 29/66795 (2013.01); H01L 29/66818 (2013.01); H01L 29/785 (2013.01); H01L 29/78615 (2013.01); H01L 21/823493 (2013.01); H01L 27/0207 (2013.01);
Abstract
A semiconductor device includes a substrate and a fin over the substrate. The fin includes a source region, a drain region, a channel region, and a biasing region. The channel region and the biasing region sandwich one of the source and drain regions. The FinFET further includes a gate over the substrate. The gate engages the fin adjacent to the channel region, thereby forming a field effect transistor (FET). The biasing region is configured to bias the FET when a voltage is applied across the biasing region and the source region.