The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 13, 2018

Filed:

Jun. 02, 2016
Applicant:

United Microelectronics Corporation, Hsinchu, TW;

Inventors:

Chih-Kai Hsu, Tainan, TW;

Yu-Hsiang Hung, Tainan, TW;

Wei-Chi Cheng, Kaohsiung, TW;

Ssu-I Fu, Kaohsiung, TW;

Jyh-Shyang Jenq, Pingtung, TW;

Chao-Hung Lin, Changhua, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/3065 (2006.01); H01L 21/02 (2006.01); H01L 29/66 (2006.01); H01L 21/308 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02636 (2013.01); H01L 21/02532 (2013.01); H01L 21/3065 (2013.01); H01L 21/3081 (2013.01); H01L 21/30625 (2013.01); H01L 29/6656 (2013.01); H01L 29/66818 (2013.01);
Abstract

The invention provides a method for fabricating a fin field effect transistor (FinFET), comprising: providing a substrate having a logic region and a large region; forming a plurality of fin structures in the logic region by removing a portion of the substrate in the logic region; forming an oxide layer on the substrate filling in-between the fin structures in the logic region; forming an first epitaxial structure in the large region by removing a portion of the substrate in the large region; exposing a portion of the fin structures and a portion of the epitaxial structure by removing a portion of the oxide layer; and forming a gate electrode on portions of the fin structures.


Find Patent Forward Citations

Loading…