The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2018

Filed:

Jun. 23, 2014
Applicant:

Applied Materials, Inc., Santa Clara, CA (US);

Inventors:

Wei Lu, Fremont, CA (US);

Zhihong Wang, Santa Clara, CA (US);

Wen-Chiang Tu, Mountain View, CA (US);

Zhefu Wang, Milpitas, CA (US);

Hassan G. Iravani, San Jose, CA (US);

Boguslaw A. Swedek, Cupertino, CA (US);

Fred C. Redeker, Fremont, CA (US);

William H. McClintock, Los Altos, CA (US);

Assignee:

Applied Materials, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/58 (2006.01); H01L 21/66 (2006.01); H01L 21/321 (2006.01);
U.S. Cl.
CPC ...
H01L 22/14 (2013.01); H01L 21/3212 (2013.01); H01L 22/26 (2013.01); H01L 22/30 (2013.01);
Abstract

A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.


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