The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2018

Filed:

Aug. 23, 2016
Applicants:

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Erhu Zheng, Shanghai, CN;

Shiliang Ji, Shanghai, CN;

Yiying Zhang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/02 (2006.01); H01L 21/768 (2006.01); H01L 21/3105 (2006.01); H01L 21/28 (2006.01); H01L 27/11524 (2017.01); H01L 27/11529 (2017.01); H01L 29/788 (2006.01); H01L 21/762 (2006.01); H01L 27/11521 (2017.01); H01L 27/11531 (2017.01); H01L 29/768 (2006.01); H01L 27/115 (2017.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02285 (2013.01); H01L 21/02118 (2013.01); H01L 21/02343 (2013.01); H01L 21/02356 (2013.01); H01L 21/28273 (2013.01); H01L 21/31051 (2013.01); H01L 21/31053 (2013.01); H01L 21/76224 (2013.01); H01L 21/76801 (2013.01); H01L 21/76826 (2013.01); H01L 27/11521 (2013.01); H01L 27/11524 (2013.01); H01L 27/11529 (2013.01); H01L 27/11531 (2013.01); H01L 29/66825 (2013.01); H01L 29/7887 (2013.01); H01L 29/665 (2013.01);
Abstract

A method for fabricating an NAND flash memory includes providing a semiconductor substrate with a core region and a peripheral region, forming a plurality of discrete gate stack structures in the core region with neighboring gate stack structures separated by a first dielectric layer. The method further includes forming a flowable dielectric layer on the first dielectric layer and the gate stack structures, and forming a solid dielectric layer through a solidification treatment process performed on the flowable dielectric layer. Voids and seams formed in the top portion of the first dielectric layer are filled by the solid dielectric layer. The method also includes removing the solid dielectric layer and a portion of the first dielectric layer to expose a top portion of the gate stack structures, and forming a metal silicide layer on each gate stack structure.


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