The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 06, 2018

Filed:

Feb. 13, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Victor W. Lee, Santa Clara, CA (US);

Daehyun Kim, San Jose, CA (US);

Yuxin Bai, San Jose, CA (US);

Shihao Ji, Portland, OR (US);

Sheng Li, Santa Clara, CA (US);

Dhiraj D. Kalamkar, Bangalore, IN;

Naveen K. Mellempudi, Bangalore, IN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/32 (2006.01); G06F 9/50 (2006.01);
U.S. Cl.
CPC ...
G06F 1/324 (2013.01); G06F 1/3296 (2013.01); G06F 9/5088 (2013.01); G06F 9/5094 (2013.01); Y02B 60/142 (2013.01); Y02B 60/162 (2013.01);
Abstract

In an embodiment, a processor a plurality of cores to independently execute instructions, the cores including a plurality of counters to store performance information, and a power controller coupled to the plurality of cores, the power controller having a logic to receive performance information from at least some of the plurality of counters, determine a number of cores to be active and a performance state for the number of cores for a next operation interval, based at least in part on the performance information and model information, and cause the number of cores to be active during the next operation interval, the performance information associated with execution of a workload on one or more of the plurality of cores. Other embodiments are described and claimed.


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