The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2018

Filed:

Dec. 29, 2016
Applicant:

Macronix International Co., Ltd., Hsinchu, TW;

Inventors:

Wei-Chih Lin, Hsinchu, TW;

Chih-Chia Hsu, Hsinchu, TW;

Yin-Fu Huang, Hsinchu, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/49 (2006.01); H01L 29/10 (2006.01); H01L 29/06 (2006.01); H01L 21/762 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 21/76205 (2013.01); H01L 29/0649 (2013.01); H01L 29/1095 (2013.01); H01L 29/4916 (2013.01); H01L 29/66681 (2013.01);
Abstract

A lateral diffused metal oxide semiconductor (LDMOS) transistor and a manufacturing method thereof are provided. A deep well region is disposed in a substrate. An isolation structure is disposed in the substrate to define a first active area and a second active area. A well region is disposed in the deep well region in the first active area. A gate is disposed on the substrate in the first active area. A gate dielectric layer is disposed between the gate and the substrate. A first doped region is disposed in the well region in the first active area and located at one side of the gate. A second doped region is disposed in the deep well region in the second active area. A conductive structure is disposed on the isolation structure, surrounds the second doped region and is connected to the gate.


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