The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2018

Filed:

Oct. 28, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Yu-Hung Cheng, Tainan, TW;

Cheng-Lung Wu, Tainan, TW;

Tung-I Lin, Tainan, TW;

Yeur-Luen Tu, Taichung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 31/0232 (2014.01); H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1463 (2013.01); H01L 27/1462 (2013.01); H01L 27/14621 (2013.01); H01L 27/14627 (2013.01); H01L 27/14645 (2013.01); H01L 27/14689 (2013.01); H01L 27/14698 (2013.01);
Abstract

A method for manufacturing a deep trench isolation (DTI) structure with a tri-layer passivation layer is provided. An etch is performed into a semiconductor substrate to form a trench. A first undoped semiconductor layer is formed by epitaxy lining surfaces of the semiconductor substrate that define the trench. A doped semiconductor layer is formed by epitaxy over and lining the first undoped semiconductor layer in the trench. A second undoped semiconductor layer is formed by epitaxy over and lining the doped semiconductor layer in the trench. A structure resulting from the method is also provided.


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