The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 20, 2018

Filed:

Dec. 16, 2016
Applicant:

Shinko Electric Industries Co., Ltd., Nagano-Shi, Nagano-Ken, JP;

Inventors:

Kei Imafuji, Nagano, JP;

Keiji Yoshizawa, Nagano, JP;

Hirokazu Yoshino, Nagano, JP;

Kenta Uchiyama, Tempe, AZ (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/498 (2006.01); H01L 21/48 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 23/49816 (2013.01); H01L 21/481 (2013.01); H01L 21/4853 (2013.01); H01L 21/76805 (2013.01); H01L 23/49811 (2013.01); H01L 23/49838 (2013.01); H01L 24/12 (2013.01); H01L 24/16 (2013.01); H01L 2224/16237 (2013.01);
Abstract

A wiring substrate includes a first wiring layer that is an uppermost wiring layer, a protective insulation layer that covers the first wiring layer, and a first through hole that extends through the protective insulation layer in a thickness-wise direction to partially expose an upper surface of the first wiring layer. The first through hole includes a recess defined in an upper surface of the protective insulation layer by a curved wall surface and an opening that extends from the upper surface of the first wiring layer to a bottom of the recess and is in communication with the recess. The opening is smaller than the recess in a plan view.


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