The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 06, 2018

Filed:

Feb. 21, 2017
Applicant:

Powertech Technology Inc., Hsinchu County, TW;

Inventors:

Jen-I Huang, Hsinchu County, TW;

Ching-Yang Chen, Hsinchu County, TW;

Assignee:

POWERTECH TECHNOLOGY INC., Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/04 (2006.01); H01L 23/485 (2006.01); H01L 23/31 (2006.01); H01L 21/56 (2006.01);
U.S. Cl.
CPC ...
H01L 23/485 (2013.01); H01L 21/563 (2013.01); H01L 21/568 (2013.01); H01L 23/3121 (2013.01);
Abstract

A fan-out semiconductor package includes a layer of adhesive covering a temporary carrier, a first redistribution layer disposed on the layer of adhesive, the first redistribution layer including a first metal layer having recessed areas. Metal pillars are plated to a first group of the recessed areas in the first metal layer. A semiconductor chip next is bonded to a second group of the recessed areas and a molding compound covers the semiconductor chip. The molding compound is then ground to expose tops of the metal pillars. A second redistribution layer including a second passivation layer adhering to the molding compound and a second metal layer covering openings exposing the tops of the metal pillars are then added.


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