The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 30, 2018

Filed:

Jul. 16, 2015
Applicant:

Advanced Semiconductor Engineering, Inc., Kaohsiung, TW;

Inventors:

Hsu-Chiang Shih, Kaohsiung, TW;

Sheng-Chi Hsieh, Kaohsiung, TW;

Chien-Hua Chen, Kaohsiung, TW;

Teck-Chong Lee, Kaohsiung, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/10 (2006.01); H01L 23/48 (2006.01); H01G 4/30 (2006.01); H01L 27/08 (2006.01); H01L 49/02 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0805 (2013.01); H01G 4/30 (2013.01); H01L 23/481 (2013.01); H01L 27/101 (2013.01); H01L 28/60 (2013.01); H01L 2224/18 (2013.01);
Abstract

A semiconductor device and a method for manufacturing the same is described. The semiconductor device includes a substrate, a first capacitor and a second capacitor. The first capacitor includes a first conductive layer, a first insulating layer and a second conductive layer. The first conductive layer is disposed on the substrate. The first insulating layer is disposed on the first conductive layer and has a first peripheral edge. The second conductive layer is disposed on the first insulating layer and has a second peripheral edge. The second capacitor includes a third conductive layer, a second insulating layer and the second conductive layer. The second insulating layer is disposed on the second conductive layer and has a third peripheral edge. The third conductive layer is disposed on the second insulating layer and has a fourth peripheral edge. The first, second, third and fourth peripheral edges are aligned with one another.


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