The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2018

Filed:

Jun. 02, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yu-Ti Su, Tainan, TW;

Han-Jen Yang, Taipei, TW;

Wun-Jie Lin, Hsin-Chu, TW;

Li-Wei Chu, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 21/06 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/861 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0262 (2013.01); H01L 27/0207 (2013.01); H01L 27/0255 (2013.01); H01L 29/0692 (2013.01); H01L 29/1095 (2013.01); H01L 29/861 (2013.01);
Abstract

An Electro-Static Discharge (ESD) protection circuit includes a plurality of groups of p-type heavily doped semiconductor strips (p+ strips) and a plurality of groups of n-type heavily doped semiconductor strips (n+ strips) forming an array having a plurality of rows and columns. In each of the rows and the columns, the plurality of groups of p+ strips and the plurality of groups of n+ strips are allocated in an alternating layout. The ESD protection circuit further includes a plurality of gate stacks, each including a first edge aligned to an edge of a group in the plurality of groups of p+ strips, and a second edge aligned to an edge of a group in the plurality of groups of n+ strips.


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