The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 23, 2018

Filed:

Dec. 24, 2014
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Bernardo Gallegos, McKinney, TX (US);

Abram Castro, Fort Worth, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01); H01L 23/538 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76838 (2013.01); H01L 21/56 (2013.01); H01L 21/76801 (2013.01); H01L 23/3128 (2013.01); H01L 23/49816 (2013.01); H01L 23/5389 (2013.01); H01L 24/19 (2013.01); H01L 24/20 (2013.01); H01L 24/16 (2013.01); H01L 2224/12105 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/9202 (2013.01); H01L 2924/15311 (2013.01);
Abstract

Methods of packaging integrated circuits are disclosed herein. In one embodiment of a method. A die having a side is provided. A conductive stud is connected to the side of the die, wherein the conductive stud has a first end that is connected to the die and an opposite second end. The die is encapsulated except for the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud enters the first side of the first dielectric layer. A conductive layer is affixed to the second side of the first dielectric layer. The second side of the conductive stud is affixed to the conductive layer using a conductive adhesive.


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