The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 09, 2018
Filed:
Mar. 30, 2015
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Walid M. Hafez, Portland, OR (US);
Chia-Hong Jan, Portland, OR (US);
Anisur Rahman, Hillsboro, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/45 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 27/092 (2006.01); H01L 29/08 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/45 (2013.01); H01L 21/823418 (2013.01); H01L 27/088 (2013.01); H01L 29/456 (2013.01); H01L 29/66659 (2013.01); H01L 29/78 (2013.01); H01L 29/7816 (2013.01); H01L 29/7835 (2013.01); H01L 27/0922 (2013.01); H01L 29/0847 (2013.01); H01L 29/495 (2013.01);
Abstract
An apparatus includes a first device with a metal gate and a drain well that experiences a series resistance that drops a drain contact voltage from 10 V to 4-6 V at a junction between the drain well and a channel under the gate. The apparatus includes an interlayer dielectric layer (ILD) disposed above and on the drain well and a salicide drain contact in the drain well. The apparatus also includes a subsequent device that is located in a region different from the first device that operates at a voltage lower than the first device.