The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 09, 2018
Filed:
May. 23, 2016
Method of forming a device including a floating gate electrode and a layer of ferroelectric material
Globalfoundries Inc., Grand Cayman, KY;
Fraunhofer Gesellschaft Zur Foerderung Der Angewandten Forschung E.v., Munich, DE;
Namlab Ggmbh, Dresden, DE;
GLOBALFOUNDRIES Inc., Grand Cayman, KY;
Fraunhofer Gesellschaft zur Foerderung der angewandted Forschung e.V., Munich, DE;
NaMLab gGmbH, Dresden, DE;
Abstract
A method disclosed herein includes providing a semiconductor structure, the semiconductor structure comprising a semiconductor substrate and a gate stack, the gate stack comprising a gate insulation material over the substrate, a floating gate electrode material over the gate insulation material, a ferroelectric transistor dielectric over the floating gate electrode material and a top electrode material over the ferroelectric transistor dielectric, performing a first patterning process to remove portions of the top electrode material and the ferroelectric transistor dielectric and performing a second patterning process after the first patterning process to remove portions of the floating gate electrode material and the gate insulation material, wherein a projected area of an upper portion of the gate structure onto a plane that is perpendicular to a thickness direction of the substrate is smaller than a projected area of the lower portion of the gate structure onto the plane.