The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 02, 2018

Filed:

Mar. 10, 2016
Applicants:

Ho-jin Lee, Seoul, KR;

Byung Lyul Park, Seoul, KR;

Jin Ho an, Seoul, KR;

Inventors:

Ho-Jin Lee, Seoul, KR;

Byung Lyul Park, Seoul, KR;

Jin Ho An, Seoul, KR;

Assignee:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 21/768 (2006.01); H01L 23/538 (2006.01); H01L 23/31 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 23/481 (2013.01); H01L 21/76831 (2013.01); H01L 21/76898 (2013.01); H01L 23/5384 (2013.01); H01L 23/5385 (2013.01); H01L 23/3128 (2013.01); H01L 23/53238 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/181 (2013.01);
Abstract

A semiconductor device includes a semiconductor substrate, a circuit layer including an interlayer insulating layer on an upper surface of the substrate, and a conductive via penetrating through the interlayer insulating layer and the substrate, and electrically connected to the circuit layer. The device further includes an insulating layer surrounding the conductive via, and located between the conductive via and the substrate and between the conductive via and interlayer insulating layer, and a buffer layer located between the insulating layer and the conductive via, and overlapping at least a portion of the interlayer insulating layer in a depth direction of the conductive via.


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