The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 26, 2017

Filed:

Nov. 23, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Rajashree Baskaran, Portland, OR (US);

Christopher M. Pelto, Beaverton, OR (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/84 (2006.01); B81B 7/00 (2006.01); B81C 1/00 (2006.01); B81B 7/02 (2006.01); B81B 3/00 (2006.01); H01L 23/00 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
B81B 7/0006 (2013.01); B81B 3/0021 (2013.01); B81B 7/02 (2013.01); B81C 1/00246 (2013.01); H01L 29/84 (2013.01); B81C 2203/0771 (2013.01); H01L 21/76898 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05025 (2013.01); H01L 2224/13025 (2013.01); H01L 2224/13124 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13184 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/81193 (2013.01); H01L 2924/1306 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1461 (2013.01);
Abstract

An integrated circuit device that comprises a single semiconductor substrate, a device layer formed on a frontside of the single semiconductor substrate, a redistribution layer formed on a backside of the single semiconductor substrate, a through silicon via (TSV) formed within the single semiconductor substrate that is electrically coupled to the device layer and to the redistribution layer, a logic-memory interface (LMI) formed on a backside of the single semiconductor substrate that is electrically coupled to the redistribution layer, and a MEMS device formed on the backside of the single semiconductor substrate that is electrically coupled to the redistribution layer.


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