The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 19, 2017

Filed:

Jun. 25, 2015
Applicants:

Nrupal Jani, Hillsboro, OR (US);

Dinesh Kumar, Beaverton, OR (US);

Christian Maciocco, Portland, OR (US);

Ren Wang, Portland, OR (US);

Neerav Parikh, Hillsboro, OR (US);

John Fastabend, Hillsboro, OR (US);

Iosif Gasparakis, Hilsboro, OR (US);

David J. Harriman, Portland, OR (US);

Patrick L. Connor, Beaverton, OR (US);

Sanjeev Jain, Chandler, AZ (US);

Inventors:

Nrupal Jani, Hillsboro, OR (US);

Dinesh Kumar, Beaverton, OR (US);

Christian Maciocco, Portland, OR (US);

Ren Wang, Portland, OR (US);

Neerav Parikh, Hillsboro, OR (US);

John Fastabend, Hillsboro, OR (US);

Iosif Gasparakis, Hilsboro, OR (US);

David J. Harriman, Portland, OR (US);

Patrick L. Connor, Beaverton, OR (US);

Sanjeev Jain, Chandler, AZ (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 12/721 (2013.01); H04L 12/26 (2006.01); H04L 12/725 (2013.01); H04L 12/803 (2013.01); H04L 12/911 (2013.01);
U.S. Cl.
CPC ...
H04L 45/44 (2013.01); H04L 43/0876 (2013.01); H04L 45/306 (2013.01); H04L 47/125 (2013.01); H04L 47/781 (2013.01);
Abstract

Devices and techniques for hardware accelerated packet processing are described herein. A device can communicate with one or more hardware switches. The device can detect characteristics of a plurality of packet streams. The device may distribute the plurality of packet streams between the one or more hardware switches and software data plane components based on the detected characteristics of the plurality of packet streams, such that at least one packet stream is designated to be processed by the one or more hardware switches. Other embodiments are also described.


Find Patent Forward Citations

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Jani, Nrupal. (2017). Apparatus and method for hardware-accelerated packet processing (U.S. Patent No. 9847936). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9847936

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