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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9847347 B1

PDFFull Text
Date of Patent:
Dec. 19, 2017

Filed:

Nov. 07, 2016

Semiconductor structure including a first transistor at a semiconductor-on-insulator region and a second transistor at a bulk region and method for the formation thereof

Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Elliot John Smith, Dresden, DE;

Nilesh Kenkare, Dresden, DE;

Nigel Chan, Dresden, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:

Amerson Law Firm, PLLC

Primary Examiner:

Karen Kusumakar

Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/51 (2006.01); H01L 29/45 (2006.01); H01L 29/417 (2006.01); H01L 29/66 (2006.01); H01L 21/84 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 21/31144 (2013.01); H01L 21/84 (2013.01); H01L 29/41783 (2013.01); H01L 29/45 (2013.01); H01L 29/51 (2013.01); H01L 29/66545 (2013.01);
Abstract

A semiconductor structure includes a substrate, a first transistor and a second transistor. The substrate includes a semiconductor-on-insulator region and a bulk region. The first transistor is provided at the semiconductor-on-insulator region and includes a first gate structure and a first channel region provided in a layer of semiconductor material over a layer of electrically insulating material. The second transistor is provided at the bulk region and includes a second gate structure and a second channel region provided in a bulk semiconductor material. A plane of an interface between the second channel region and the second gate structure is not above a plane of an interface between the bulk semiconductor material and the layer of electrically insulating material in the semiconductor-on-insulator region. A height of the second gate structure is greater than a height of the first gate structure.

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