The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2017

Filed:

Nov. 17, 2016
Applicant:

Powertech Technology Inc., Hsinchu County, TW;

Inventor:

Chia-Jen Chou, Hsinchu County, TW;

Assignee:

POWERTECH TECHNOLOGY INC., Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/12 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/367 (2006.01); H01L 23/373 (2006.01); H01L 23/29 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 23/293 (2013.01); H01L 23/3135 (2013.01); H01L 23/3672 (2013.01); H01L 23/3736 (2013.01); H01L 23/3737 (2013.01); H01L 23/49816 (2013.01); H01L 23/49822 (2013.01); H01L 23/49827 (2013.01); H01L 24/48 (2013.01); H01L 2224/48227 (2013.01);
Abstract

A heat-dissipating semiconductor package includes a substrate, a chip, a first encapsulation body, a second encapsulation body and a heat sink. The substrate has an inner surface. The chip is disposed on the inner surface of the substrate. The first encapsulation body is formed on the inner surface of the substrate and encapsulates the chip. The second encapsulation body is formed on the first encapsulation body and a periphery area of the inner surface to encapsulate sidewalls and a top surface of the first encapsulation body and cover the periphery area of the inner surface. Wherein, the Young's modulus of the second encapsulation body is less than the Young's modulus of the first encapsulation body. The heat sink is attached to the second encapsulation body. Thereby, the design of the heat-dissipating semiconductor package utilizes multiple encapsulation bodies to reduce the package warpage after installing the heat sink.


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