The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2017

Filed:

Sep. 18, 2015
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Carl Z. Zhou, Plano, TX (US);

John A. Rodriguez, Dallas, TX (US);

Richard A. Bailey, Richardson, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/50 (2006.01); G11C 11/22 (2006.01);
U.S. Cl.
CPC ...
G11C 29/50016 (2013.01); G11C 29/50008 (2013.01); G11C 11/2275 (2013.01);
Abstract

A data retention reliability screen of integrated circuits including ferroelectric random access memory (FRAM) arrays. Sampled groups of cells in the FRAM array are tested at various reference voltage levels, after programming to a high polarization capacitance data state and a relaxation time at an elevated temperature. Fail bit counts of the sample groups at the various reference voltage levels are used to derive a test reference voltage, against which all of the FRAM cells in the integrated circuit are then tested after preconditioning (i.e., programming) and another relaxation interval at the elevated temperature, to determine those cells in the integrated circuit that are vulnerable to long-term data retention failure.


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