The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 12, 2017

Filed:

Aug. 17, 2015
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

M. Sultan M. Siddiqui, Uttar Pradesh, IN;

Shailendra Sharad, Uttar Pradesh, IN;

Hemant Vats, New Delhi, IN;

Amit Khanuja, New Delhi, IN;

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/22 (2006.01); G11C 11/419 (2006.01); G11C 11/418 (2006.01); G11C 8/08 (2006.01);
U.S. Cl.
CPC ...
G11C 11/419 (2013.01); G11C 7/227 (2013.01); G11C 8/08 (2013.01); G11C 11/418 (2013.01); G11C 2207/229 (2013.01);
Abstract

An integrated circuit for storing data comprises a memory cell array comprising a plurality of bit cells (BC, . . . , BCn) comprising a first and a second one of the bit cells (BC, BC) having a static random access memory architecture. The first and the second bit cells (BC, BC) are coupled to a common wordline (WL_TOP) and are arranged in different columns (C, C) of the memory cell array (). During a write access to the first bit cell (BC), the first bit cell (BC) undergoes a write operation, whereas the second bit cell (BC) is a half-selected bit cell which undergoes a pseudo read operation. The integrated circuit uses a two-phase write scheme to improve the write-ability in low operating voltage environment.


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