The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2017

Filed:

Apr. 19, 2016
Applicant:

United Microelectronics Corp., Hsinchu, TW;

Inventors:

Aaron Chen, Singapore, SG;

Chi Ren, Singapore, SG;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 27/11521 (2017.01); H01L 29/788 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11521 (2013.01); H01L 29/0649 (2013.01); H01L 29/4236 (2013.01); H01L 29/6656 (2013.01); H01L 29/66545 (2013.01); H01L 29/66825 (2013.01); H01L 29/7881 (2013.01);
Abstract

A semiconductor device with split gate flash memory cell structure includes a substrate having a first area and a second area, at least a first cell formed in the first area and at least a second cell formed in the second area. The first cell includes a first dielectric layer formed on the substrate, a floating gate (FG), a word line and an erase gate (EG) formed on the first dielectric layer, an interlayer dielectric (ILD) layer, an inter-gate dielectric layer and a control gate (CG). The FG is positioned between the word line and the EG, and the ILD layer is formed on the word line and the EG, wherein the ILD layer has a trench exposing the FG. The inter-gate dielectric layer is formed in the trench as a liner, and the CG formed in the trench is surrounded by the inter-gate dielectric layer.


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