The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2017

Filed:

Jun. 01, 2016
Applicant:

Infineon Technologies Austria Ag, Villach, AT;

Inventors:

Thomas Basler, Riemerling, DE;

Edward Fuergut, Dasing, DE;

Christian Kasztelan, Munich, DE;

Ralf Otremba, Kaufbeuren, DE;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/10 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 25/07 (2006.01); H01L 23/36 (2006.01); H01L 23/373 (2006.01); H01L 23/495 (2006.01); H01L 23/498 (2006.01); H01L 23/24 (2006.01); H01L 23/40 (2006.01);
U.S. Cl.
CPC ...
H01L 21/565 (2013.01); H01L 23/24 (2013.01); H01L 23/36 (2013.01); H01L 23/3737 (2013.01); H01L 23/4006 (2013.01); H01L 23/49524 (2013.01); H01L 23/49562 (2013.01); H01L 23/49861 (2013.01); H01L 24/48 (2013.01); H01L 25/074 (2013.01); H01L 23/4093 (2013.01); H01L 2224/4846 (2013.01); H01L 2225/06589 (2013.01); H01L 2924/181 (2013.01);
Abstract

A semiconductor power package includes a pre-molded chip housing and an electrically conducting chip carrier cast-in-place in the pre-molded chip housing. The semiconductor power package further includes a power semiconductor chip bonded on the electrically conducting chip carrier. A covering material is provided to embed the power semiconductor chip. The covering material has an elastic modulus less than an elastic modulus of a material of the pre-molded chip housing and/or a thermal conductivity greater than a thermal conductivity of the material of the pre-molded chip housing and/or a temperature stability greater than a temperature stability of the pre-molded chip housing.


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