The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 05, 2017

Filed:

May. 17, 2016
Applicants:

International Business Machines Corporation, Armonk, NY (US);

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Andrew M. Greene, Albany, NY (US);

Ryan O. Jung, Glenmont, NY (US);

Ruilong Xie, Niskayuna, NY (US);

Assignees:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 21/283 (2006.01); H01L 21/311 (2006.01); H01L 21/28 (2006.01); H01L 27/02 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 21/283 (2013.01); H01L 21/28017 (2013.01); H01L 21/31111 (2013.01); H01L 27/0207 (2013.01); H01L 29/66553 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01);
Abstract

A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.


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