The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2017

Filed:

Nov. 19, 2009
Applicants:

Philippe Renaud, Cugnaux, FR;

Bruce Green, Gilbert, AZ (US);

Inventors:

Philippe Renaud, Cugnaux, FR;

Bruce Green, Gilbert, AZ (US);

Assignee:

NXP USA, INC., Austin, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/778 (2006.01); H01L 21/8252 (2006.01); H01L 27/06 (2006.01); H01L 29/66 (2006.01); H01L 29/20 (2006.01); H01L 29/417 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7786 (2013.01); H01L 21/8252 (2013.01); H01L 27/0605 (2013.01); H01L 29/66462 (2013.01); H01L 29/7788 (2013.01); H01L 29/2003 (2013.01); H01L 29/417 (2013.01);
Abstract

A vertical power transistor device comprises: a substrate formed from a III-V semiconductor material and a multi-layer stack at least partially accommodated in the substrate. The multi-layer stack comprises: a semi-insulating layer disposed adjacent the substrate and a first layer formed from a first III-V semiconductor material and disposed adjacent the semi-insulating layer. The multi-layer stack also comprises a second layer formed from a second III-V semiconductor material disposed adjacent the first layer and a heterojunction is formed at an interface of the first and second layers.


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