The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2017

Filed:

Jan. 31, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Aleksandar Aleksov, Chandler, AZ (US);

Tony Dambrauskas, Chandler, AZ (US);

Danish Faruqui, Chandler, AZ (US);

Mark S. Hlad, Chandler, AZ (US);

Edward R. Prack, Phoenix, AZ (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/58 (2006.01); H01L 23/00 (2006.01); H01L 21/78 (2006.01); H01L 21/02 (2006.01); H01L 21/027 (2006.01); H01L 21/311 (2006.01); H01L 25/065 (2006.01); H01L 25/00 (2006.01); H01L 21/683 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 24/11 (2013.01); H01L 21/0273 (2013.01); H01L 21/02118 (2013.01); H01L 21/02263 (2013.01); H01L 21/31144 (2013.01); H01L 21/6835 (2013.01); H01L 21/78 (2013.01); H01L 24/81 (2013.01); H01L 24/94 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 21/76898 (2013.01); H01L 24/14 (2013.01); H01L 2221/68327 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/1147 (2013.01); H01L 2224/1162 (2013.01); H01L 2224/1191 (2013.01); H01L 2224/11849 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/16146 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/81024 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81192 (2013.01); H01L 2224/81207 (2013.01); H01L 2224/81375 (2013.01); H01L 2225/06513 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01);
Abstract

Electronic assemblies and their manufacture are described. One embodiment relates to a method including depositing an organic thin film layer on metal bumps on a semiconductor wafer, the organic thin film layer also being formed on a surface adjacent to the metal bumps on the wafer. The wafer is diced into a plurality of semiconductor die structures, the die structures including the organic thin film layer. The semiconductor die structures are attached to substrates, wherein the attaching includes forming a solder bond between the metal bumps on a die structure and bonding pads on a substrate, and wherein the solder bond extends through the organic thin film layer. The organic thin film layer is then exposed to a plasma. Other embodiments are described and claimed.


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