The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 21, 2017

Filed:

Jan. 21, 2014
Applicant:

Lam Research Corporation, Fremont, CA (US);

Inventors:

Daniel Mark Dinneen, Tigard, OR (US);

Steven T. Mayer, Lake Oswego, OR (US);

Assignee:

Lam Research Corporation, Fremont, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
C25D 17/12 (2006.01); C25D 21/12 (2006.01); C25D 17/16 (2006.01); H01L 21/67 (2006.01); H01L 21/66 (2006.01); C25D 3/38 (2006.01); C25D 7/12 (2006.01); C25D 17/00 (2006.01);
U.S. Cl.
CPC ...
C25D 17/16 (2013.01); C25D 3/38 (2013.01); C25D 7/123 (2013.01); C25D 17/001 (2013.01); C25D 21/12 (2013.01); H01L 21/67011 (2013.01); H01L 22/12 (2013.01);
Abstract

Disclosed herein are methods and apparatuses for electroplating which employ seed layer detection. Such methods and related apparatuses may operate by selecting a wafer for processing, measuring from its surface one or more in-process color signals having one or more color components, calculating one or more metrics, each metric indicative of the difference between one of the in-process color signals and a corresponding set of reference color signals, determining whether an acceptable seed layer is present on the wafer surface based on whether a predetermined number of the one or more metrics are within an associated predetermined range which individually corresponds to that metric, and either electroplating the wafer when an acceptable seed layer is present or otherwise designating the wafer unacceptable for electroplating. The foregoing may then be repeated for one or more additional wafers to electroplate multiple wafers from a set of wafers.


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