The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2017

Filed:

Dec. 19, 2016
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Inventors:

Kazuaki Ohshima, Kanagawa, JP;

Kiyoshi Kato, Kanagawa, JP;

Tomoaki Atsumi, Kanagawa, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/06 (2006.01); H01L 27/105 (2006.01); H01L 27/12 (2006.01); H01L 27/11 (2006.01); H01L 27/108 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); G11C 5/14 (2006.01); G06F 1/32 (2006.01); H01L 29/786 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1052 (2013.01); G06F 1/3275 (2013.01); G11C 5/06 (2013.01); G11C 5/14 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/10805 (2013.01); H01L 27/1108 (2013.01); H01L 27/1207 (2013.01); H01L 27/1211 (2013.01); H01L 27/1225 (2013.01); H01L 29/7851 (2013.01); H01L 29/7869 (2013.01); H01L 29/78648 (2013.01);
Abstract

Provided is a semiconductor device capable of holding data for a long period. The semiconductor device includes first to third transistors, a capacitor, and a circuit. The third transistor includes a first gate and a second gate. A gate of the first transistor is electrically connected to a first terminal of the capacitor. A first terminal of the first transistor is electrically connected to the second gate. A second terminal of the first transistor is electrically connected to the circuit. A gate of second transistor is electrically connected to a first terminal of the second transistor. A first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to a first terminal of the capacitor. The circuit is configured to generate a negative potential. A channel formation region of the first transistor preferably includes an oxide semiconductor.


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