The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2017

Filed:

Oct. 31, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Yung-Yao Wang, Tainan, TW;

Ying-Han Chiou, Tainan, TW;

Ling-Sung Wang, Tainan, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01); H01L 23/532 (2006.01); H01L 23/522 (2006.01); H01L 21/768 (2006.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/7681 (2013.01); H01L 21/7684 (2013.01); H01L 21/76801 (2013.01); H01L 21/76828 (2013.01); H01L 21/76829 (2013.01); H01L 21/76877 (2013.01); H01L 22/12 (2013.01); H01L 23/522 (2013.01); H01L 23/5226 (2013.01); H01L 23/53228 (2013.01); H01L 23/53295 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 2224/02206 (2013.01); H01L 2224/02215 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05124 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/05166 (2013.01); H01L 2224/05624 (2013.01); H01L 2224/13026 (2013.01); H01L 2224/13101 (2013.01); H01L 2224/13147 (2013.01); H01L 2924/05042 (2013.01); H01L 2924/05442 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/3511 (2013.01);
Abstract

A method includes forming a low-k dielectric layer over a substrate of a wafer, forming a first dielectric layer over the low-k dielectric layer, forming a second dielectric layer over the first dielectric layer, forming a stress tuning dielectric layer over the second dielectric layer, forming an opening in the stress tuning dielectric layer to expose a top surface of the second dielectric layer, and etching the stress tuning dielectric layer and the second dielectric layer to form a trench. The formation of the opening and the etching of the stress tuning dielectric layer are performed in separate etching steps. The method further includes etching the first dielectric layer to form a via opening connected to the trench, and filling the trench and the via opening to form a metal line and a via, respectively.


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