The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2017

Filed:

Aug. 01, 2016
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Tsung-Min Huang, Taichung, TW;

Chung-Ju Lee, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/768 (2006.01); H01L 23/532 (2006.01); H01L 21/321 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 23/53238 (2013.01); H01L 21/321 (2013.01); H01L 21/32136 (2013.01); H01L 21/76802 (2013.01); H01L 21/76834 (2013.01); H01L 21/76841 (2013.01); H01L 21/76847 (2013.01); H01L 21/76883 (2013.01); H01L 21/76885 (2013.01); H01L 23/53223 (2013.01); H01L 23/53233 (2013.01); H01L 23/53266 (2013.01); H01L 21/7682 (2013.01); H01L 23/5329 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A method of fabricating a semiconductor device comprises forming a first dielectric material layer on a semiconductor substrate. The first dielectric material layer is patterned to form a plurality of vias therein. A metal layer is formed on the first dielectric material layer, wherein the metal layer fills the plurality of vias. The metal layer is etched such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal features aligned with the plurality of vias respectively. A self-assembled monolayer film is formed on surfaces of the plurality of metal features.


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