The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 14, 2017

Filed:

Aug. 15, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd, Hsinchu, TW;

Inventors:

Yi-Cheng Chao, Lukang Township, Changhua County, TW;

Chai-Wei Chang, New Taipei, TW;

Po-Chi Wu, Zhubei, TW;

Jung-Jui Li, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 27/00 (2006.01); H01L 29/00 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 21/308 (2006.01); H01L 21/762 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823431 (2013.01); H01L 21/3081 (2013.01); H01L 21/76224 (2013.01); H01L 21/823456 (2013.01); H01L 27/0886 (2013.01); H01L 29/0642 (2013.01); H01L 29/0657 (2013.01); H01L 29/6681 (2013.01); H01L 21/823481 (2013.01);
Abstract

Methods for forming the fin field effect transistor (FinFET) device structure are provided. The method includes forming first fin structures and second fin structures on a first region and a second region of a substrate, respectively, and a number of the first fin structures is greater than a number of the second fin structures. The method also includes forming a sacrificial layer on the first fin structures and the second fin structures and performing an etching process to the sacrificial layer to form an isolation structure on the substrate.


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