The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 2017
Filed:
May. 19, 2014
Applicant:
Applied Materials, Inc., Santa Clara, CA (US);
Inventors:
Assignee:
APPLIED MATERIALS, INC., Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 21/02 (2006.01); C23C 16/24 (2006.01); C23C 16/56 (2006.01);
U.S. Cl.
CPC ...
H01L 21/02595 (2013.01); C23C 16/24 (2013.01); C23C 16/56 (2013.01); H01L 21/0262 (2013.01); H01L 21/02488 (2013.01); H01L 21/02502 (2013.01); H01L 21/02532 (2013.01); H01L 21/02686 (2013.01); H01L 21/02592 (2013.01);
Abstract
The embodiments described herein generally relate to methods for forming an amorphous silicon structure that may be used in thin film transistor devices. In embodiments disclosed herein, the amorphous silicon layer is deposited using a silicon-based gas with an activation gas comprising a high concentration of inert gas and a low concentration of hydrogen-based gas. The activation gas combination allows for a good deposition profile of the amorphous silicon layer from the edge of the shadow frame which is translated to the polycrystalline silicon layer post-annealing.