The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 14, 2017
Filed:
Aug. 31, 2015
Globalfoundries Inc., Grand Cayman, KY;
Guo Xiang Ning, Ballston Lake, NY (US);
Yuping Ren, Clifton Park, NY (US);
David Power, Malta, NY (US);
Lalit Shokeen, Clifton Park, NY (US);
Chin Teong Lim, Clifton Park, NY (US);
Paul W. Ackmann, Gansevoort, NY (US);
Xiang Hu, Clifton Park, NY (US);
GLOBALFOUNDRIES INC., Grand Cayman, KY;
Abstract
A method and apparatus for generating a final dielectric etch compensation table and a final hard mask etch compensation table for either OPC or MPC process flows are provided. Embodiments include performing an overlap pattern classification on a wafer; calibrating a dielectric etch bias or a hard mask etch bias based on the pattern classification; comparing either a CD overlap of a via layer with a metal layer and a CD overlap of the via layer with a lower connecting metal layer or a CD overlap of the metal layer with an upper connecting via layer and a CD overlap of the metal layer with the via layer against a criteria; outputting final dielectric etch compensation and hard mask etch compensation tables to either OPC or MPC process flows; and repeating the steps of calibrating, comparing, and outputting for either the via layer or metal layer remaining.