The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2017

Filed:

Sep. 06, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd, Hsinchu, TW;

Inventors:

Che-Cheng Chang, New Taipei, TW;

Chih-Han Lin, Hsinchu, TW;

Chen-Hsiang Lu, Hsinchu, TW;

Wei-Ting Chen, Hsinchu, TW;

Yu-Cheng Liu, Hsinchu County, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/3205 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/49 (2006.01); H01L 21/28 (2006.01); H01L 21/311 (2006.01); H01L 23/522 (2006.01); H01L 29/51 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6653 (2013.01); H01L 21/28008 (2013.01); H01L 21/28247 (2013.01); H01L 21/31116 (2013.01); H01L 23/5226 (2013.01); H01L 29/4966 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01); H01L 29/517 (2013.01); H01L 29/7848 (2013.01);
Abstract

One or more formation methods of a semiconductor device structure are provided. The method includes forming a dummy gate stack over a semiconductor substrate and forming spacer elements over sidewalls of the dummy gate stack. The method also includes removing the dummy gate stack to form a recess between the spacer elements. The method further includes partially removing the spacer elements such that an upper portion of the recess becomes wider. In addition, the method includes forming a metal gate stack in the recess and forming a protection element over the metal gate stack to fill the recess.


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