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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9812546 B1

PDFFull Text
Date of Patent:
Nov. 07, 2017

Filed:

Jan. 09, 2017

Tungsten gates for non-planar transistors

Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Sameer S. Pradhan, Portland, OR (US);

Daniel B. Bergstrom, Lake Oswego, OR (US);

Jin-Sung Chun, Hillsboro, OR (US);

Julia Chiu, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:

Green, Howard and Mughal LLP

Primary Examiner:

Daniel Shook

Int. Cl.
CPC ...
H01L 29/49 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/40 (2006.01); C23C 14/06 (2006.01); H01L 29/417 (2006.01); H01L 23/522 (2006.01); H01L 21/28 (2006.01); H01L 21/8238 (2006.01); H01L 27/092 (2006.01);
U.S. Cl.
CPC ...
H01L 29/4966 (2013.01); C23C 14/0635 (2013.01); C23C 14/0652 (2013.01); H01L 21/28088 (2013.01); H01L 21/823821 (2013.01); H01L 21/823842 (2013.01); H01L 23/5226 (2013.01); H01L 27/0924 (2013.01); H01L 29/401 (2013.01); H01L 29/41775 (2013.01); H01L 29/41791 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of gates within non-planar NMOS transistors, wherein an NMOS work-function material, such as a composition of aluminum, titanium, and carbon, may be used in conjunction with a titanium-containing gate fill barrier to facilitate the use of a tungsten-containing conductive material in the formation of a gate electrode of the non-planar NMOS transistor gate.

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