The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 07, 2017

Filed:

Jul. 21, 2016
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Ching-Feng Fu, Taichung, TW;

Yu-Chan Yen, Taipei, TW;

Chia-Ying Lee, New Taipei, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/45 (2006.01); H01L 29/417 (2006.01); H01L 21/768 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 21/3105 (2006.01); H01L 29/78 (2006.01); H01L 29/165 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01); H01L 21/321 (2006.01); H01L 29/08 (2006.01); H01L 29/267 (2006.01);
U.S. Cl.
CPC ...
H01L 29/41783 (2013.01); H01L 21/02532 (2013.01); H01L 21/02592 (2013.01); H01L 21/31055 (2013.01); H01L 21/31111 (2013.01); H01L 21/32115 (2013.01); H01L 21/76879 (2013.01); H01L 21/76897 (2013.01); H01L 29/0847 (2013.01); H01L 29/165 (2013.01); H01L 29/267 (2013.01); H01L 29/4175 (2013.01); H01L 29/42364 (2013.01); H01L 29/45 (2013.01); H01L 29/6681 (2013.01); H01L 29/66545 (2013.01); H01L 29/66606 (2013.01); H01L 29/66795 (2013.01); H01L 29/78 (2013.01); H01L 29/7848 (2013.01); H01L 29/7851 (2013.01);
Abstract

The present disclosure relate to a method to an integrated chip having a source/drain self-aligned contact to a transistor or other semiconductor device. In some embodiments, the integrated chip has a pair of gate structures including a gate electrode arranged over a substrate and an insulating material arranged over the gate electrode. A source/drain region is arranged within the substrate between the pair of gate structures. An etch stop layer is arranged along sidewalls of the pair of gate structures and over the source/drain region, and a dielectric layer is over the insulating material. A source/drain contact is arranged over the insulating material and the etch stop layer and is separated from the sidewalls of the pair of gate structures by the etch stop layer. The source/drain contact is electrically coupled to the source/drain region.


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