The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 31, 2017
Filed:
Oct. 02, 2013
Applicant:
Infineon Technologies Austria Ag, Villach, AT;
Inventors:
Assignee:
Infineon Technologies Austria AG, Villach, AT;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 1/00 (2006.01); H05K 1/18 (2006.01); H05K 7/00 (2006.01); H01L 23/538 (2006.01); H01L 21/02 (2006.01); H01L 23/00 (2006.01); H01L 23/433 (2006.01); H01L 23/495 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/5384 (2013.01); H01L 21/02104 (2013.01); H01L 23/4334 (2013.01); H01L 23/49513 (2013.01); H01L 23/49524 (2013.01); H01L 23/49541 (2013.01); H01L 23/49575 (2013.01); H01L 24/33 (2013.01); H01L 24/36 (2013.01); H01L 24/40 (2013.01); H01L 24/84 (2013.01); H01L 23/3107 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/4007 (2013.01); H01L 2224/40095 (2013.01); H01L 2224/40137 (2013.01); H01L 2224/40245 (2013.01); H01L 2224/48247 (2013.01); H01L 2224/49171 (2013.01); H01L 2224/73221 (2013.01); H01L 2224/83192 (2013.01); H01L 2224/92246 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/181 (2013.01); Y10T 29/49105 (2015.01);
Abstract
An electronic device comprising a first substrate, a second substrate, a first semiconductor chip comprising a transistor, comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, and a second semiconductor chip comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, wherein the first semiconductor chip comprises a via electrically coupling a first transistor terminal at its first mounting surface with a second transistor terminal at its second mounting surface.