The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 31, 2017
Filed:
Nov. 20, 2015
Applicant:
Freescale Semiconductor, Inc., Austin, TX (US);
Inventors:
Weiwei Sang, Suzhou, CN;
Wanggen Zhang, Suzhou, CN;
Assignee:
NXP USA,INC., Austin, TX (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G11C 29/40 (2006.01); G11C 29/44 (2006.01); G01R 31/3185 (2006.01); G11C 29/32 (2006.01);
U.S. Cl.
CPC ...
G11C 29/40 (2013.01); G01R 31/318597 (2013.01); G11C 29/32 (2013.01); G11C 29/44 (2013.01);
Abstract
An integrated circuit (IC) having a memory for storing data also has a memory built in self-test (MBIST) unit coupled to the memory for testing an operation of the memory. A test interface provides test data. Flip-flops of the IC are connected together into at least one serial scan chain. The test interface unit receives test data including MBIST configuration data. The MBIST unit, in a first mode, tests the memory based on the MBIST configuration data at least partly in parallel with a scan test using the scan chain. Thus, both the memory and the logic circuitry can be tested in parallel.