The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 31, 2017

Filed:

Dec. 05, 2013
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Nathaniel J. August, Portland, OR (US);

Pulkit Jain, Hillsboro, OR (US);

Stefan Rusu, Sunnyvale, CA (US);

Fatih Hamzaoglu, Portland, OR (US);

Rangharajan Venkatesan, Hillsboro, OR (US);

Muhammad Khellah, Tigard, OR (US);

Charles Augustine, West Lafayette, IN (US);

Carlos Tokunaga, Hillsboro, OR (US);

James W. Tschanz, Portland, OR (US);

Yih Wang, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 13/00 (2006.01); G11C 14/00 (2006.01); G11C 11/16 (2006.01);
U.S. Cl.
CPC ...
G11C 13/0061 (2013.01); G11C 11/161 (2013.01); G11C 11/1657 (2013.01); G11C 11/1659 (2013.01); G11C 11/1675 (2013.01); G11C 13/0011 (2013.01); G11C 13/0014 (2013.01); G11C 14/009 (2013.01); G11C 14/0081 (2013.01); G11C 11/1693 (2013.01);
Abstract

Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.


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