The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2017

Filed:

Oct. 23, 2014
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;

Inventors:

Ming-Jhih Kuo, Hsinchu County, TW;

Yu-Hsien Lin, Hsinchu, TW;

Hung-Chang Hsieh, Hsinchu, TW;

Jhun Hua Chen, Changhua County, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8234 (2006.01); H01L 21/311 (2006.01); H01L 27/088 (2006.01); H01L 29/49 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H01L 21/768 (2006.01); H01L 29/165 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823475 (2013.01); H01L 21/76829 (2013.01); H01L 21/76895 (2013.01); H01L 21/76897 (2013.01); H01L 21/823468 (2013.01); H01L 29/6656 (2013.01); H01L 29/66636 (2013.01); H01L 27/088 (2013.01); H01L 29/165 (2013.01); H01L 29/517 (2013.01);
Abstract

A method of fabricating a semiconductor device is disclosed. The method includes forming a gate structure over a substrate. The gate structure includes a first hard mask layer. The method also includes forming a source/drain (S/D) feature in the substrate adjacent to the gate structure, forming a sidewall spacer along sidewalls of the gate structure. The sidewall spacer has an outer edge at its upper portion facing away from the gate structure. The method also includes forming a second spacer along sidewalls of the gate structure and along the outer edge of the sidewall spacer, forming dielectric layers over the gate structure, forming a trench extending through the dielectric layers to expose the source/drain feature while the gate structure is protected by the first hard mask layer and the sidewall spacer with the second spacer. The method also includes forming a contact feature in the trench.


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