The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2017

Filed:

Aug. 17, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Chan-Hoon Park, Osan-si, KR;

Dong-Chan Kim, Seoul, KR;

Masayuki Tomoyasu, Seongnam-si, KR;

Je-Woo Han, Hwaseong-si, KR;

Assignee:

SAMSUNG ELECTRONICS CO., LTD., Samsung-ro, Yeongtong-gu, Suwon-si, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/338 (2006.01); H01L 21/768 (2006.01); H01L 21/66 (2006.01); H01L 21/68 (2006.01); H01L 21/8234 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76897 (2013.01); H01L 21/682 (2013.01); H01L 21/76805 (2013.01); H01L 21/823431 (2013.01); H01L 21/823437 (2013.01); H01L 21/823468 (2013.01); H01L 21/823475 (2013.01); H01L 22/12 (2013.01);
Abstract

A method for fabricating a semiconductor device is disclosed. The method includes forming a first interlayer insulating layer including a first trench that is defined by a first gate spacer and a second trench that is defined by a second gate spacer on a substrate, forming a first gate electrode that fills a part of the first trench and a second gate electrode that fills a part of the second trench, forming a first capping pattern that fills the remainder of the first trench on the first gate electrode, forming a second capping pattern that fills the remainder of the second trench on the second gate electrode, forming a second interlayer insulating layer that covers the first gate spacer and the second gate spacer on the first interlayer insulating layer, forming a third interlayer insulating layer on the second interlayer insulating layer and forming a contact hole that penetrates the third interlayer insulating layer and the second interlayer insulating layer between the first gate electrode and the second gate electrode.


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