The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2017

Filed:

Dec. 28, 2015
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Mani Ayyar, Cupertino, CA (US);

Eric Richard Delano, Fort Collins, CO (US);

Ioannis Y. Schoinas, Portland, OR (US);

Akhilesh Kumar, Sunnyvale, CA (US);

Doddaballapur Jayasimha, Sunnyvale, CA (US);

Jose A. Vargas, Rescue, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/445 (2006.01); G06F 13/00 (2006.01); G06F 9/50 (2006.01); G06F 13/40 (2006.01); G06F 13/24 (2006.01);
U.S. Cl.
CPC ...
G06F 9/44505 (2013.01); G06F 9/50 (2013.01); G06F 9/5011 (2013.01); G06F 13/00 (2013.01); G06F 13/24 (2013.01); G06F 13/409 (2013.01); G06F 13/4081 (2013.01);
Abstract

A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.


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