The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 24, 2017

Filed:

Nov. 20, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Joshua T. Smith, Croton on Hudson, NY (US);

Cornelia K. Tsang, Medford, MA (US);

Chao Wang, Chandler, AZ (US);

Benjamin H. Wunsch, Mt. Kisco, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
B29C 65/00 (2006.01); B31B 1/60 (2006.01); B32B 37/00 (2006.01); H01L 21/20 (2006.01); B01L 3/00 (2006.01); B81C 1/00 (2006.01); B81B 7/00 (2006.01); G01N 15/10 (2006.01);
U.S. Cl.
CPC ...
B01L 3/502707 (2013.01); B01L 3/502715 (2013.01); B01L 3/502761 (2013.01); B81B 7/0061 (2013.01); B81C 1/00309 (2013.01); G01N 15/10 (2013.01); B01L 2200/0689 (2013.01); B01L 2200/12 (2013.01); B01L 2300/0887 (2013.01); B01L 2300/0896 (2013.01); B01L 2300/12 (2013.01); B81B 2201/058 (2013.01); B81B 2203/0338 (2013.01); B81C 2203/0118 (2013.01); G01N 2015/1081 (2013.01);
Abstract

Techniques for use of wafer bonding techniques for sealing of microfluidic chips are provided. In one aspect, a wafer bonding sealing method includes the steps of: forming a first oxide layer coating surfaces of a first wafer, the first wafer having at least one fluidic chip; forming a second oxide layer on a second wafer; and bonding the first wafer to the second wafer via an oxide-to-oxide bond between the first oxide layer and the second oxide layer to form a bonded wafer pair, wherein the second oxide layer seals the at least one fluidic chip on the first wafer. The second wafer can be at least partially removed after performing the bonding, and fluidic ports may be formed in the second oxide layer. A fluidic chip device is also provided.


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