The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2017

Filed:

Mar. 10, 2017
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Hans-Juergen Thees, Dresden, DE;

Peter Baars, Dredsen, DE;

Assignee:

GLOBALFOUNDRIES Inc., Grand Cayman, KY;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 27/12 (2006.01); H01L 29/417 (2006.01); H01L 27/092 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1203 (2013.01); H01L 27/0922 (2013.01); H01L 29/16 (2013.01); H01L 29/41783 (2013.01);
Abstract

A semiconductor device includes an SOI substrate and a transistor device positioned in and above the SOI substrate. The SOI substrate includes a semiconductor bulk substrate, a buried insulation layer above the semiconductor bulk substrate, and a semiconductor layer above the buried insulation layer. The transistor device includes a gate structure having a gate electrode and a first cap layer covering upper and sidewall surfaces of the gate electrode. An oxide liner covers sidewalls of the gate structure and a second cap layer covers the oxide liner. A recess is located adjacent to the gate structure and is at least partially defined by an upper surface of the semiconductor layer, a bottom surface of the second cap layer and at least part of the oxide liner. Raised source/drain regions are positioned above the semiconductor layer and portions of the raised source/drain regions are positioned in the recess.


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