The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 17, 2017

Filed:

Mar. 30, 2016
Applicant:

Triquint Semiconductor, Inc., Hillsboro, OR (US);

Inventors:

Tarak A. Railkar, Plano, TX (US);

Kevin J. Anderson, Plano, TX (US);

Assignee:

Qorvo US, Inc., Greensboro, NC (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 24/81 (2013.01); H01L 24/09 (2013.01); H01L 24/17 (2013.01); H01L 2224/0901 (2013.01); H01L 2224/0912 (2013.01); H01L 2224/1705 (2013.01); H01L 2224/17106 (2013.01); H01L 2224/812 (2013.01); H01L 2224/81375 (2013.01); H01L 2224/81385 (2013.01); H01L 2224/81815 (2013.01);
Abstract

The present disclosure relates to a flip-chip package with a hollow-cavity and reinforced interconnects, and a process for making the same. The disclosed flip-chip package includes a substrate, a reinforcement layer over an upper surface of the substrate, a flip-chip die attached to the upper surface of the substrate by interconnects through the reinforcement layer, an air cavity formed between the substrate and the flip-chip die, and a protective layer encapsulating the flip-chip die and defining a perimeter of the air cavity. Herein, a first portion of each interconnect is encapsulated by the reinforcement layer and a second portion of each interconnect is exposed to the air cavity. The reinforcement layer provides reinforcement to each interconnect.


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