The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 17, 2017
Filed:
Jun. 13, 2016
International Business Machines Corporation, Armonk, NY (US);
Paul A. Bunce, Poughkeepsie, NY (US);
Yuen H. Chan, Poughkeepsie, NY (US);
John D. Davis, Wallkill, NY (US);
Silke Penth, Holzgerlingen, DE;
David E. Schmitt, Rochester, MN (US);
Tobias Werner, Weil im Schoenbuch, DE;
Brian J. Yavoich, Highland, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A memory array can include a global evaluation circuit, a local evaluation circuit for evaluating a voltage level of a local bit line and a wake transistor configured to connect an output of the local evaluation circuit to a global bit line (GBL) of the global evaluation circuit. The global evaluation circuit can include a holding circuit. The wake transistor can be turned on in response to a read signal, and remain on while the GBL is precharged to a logical 'high' voltage. Memory cells connected to the at least one local bit line can be addressed, and the local bit line can be pulled to a logical 'low' voltage for a first time period. The GBL can be pulled to a logical low voltage for a second time period, and the holding circuit polarity can be reversed during a third time period.